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PC87413 датащи(PDF) 103 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 103 Page - National Semiconductor (TI) |
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103 / 257 page ![]() 5.0 X-Bus Extension (Continued) Revision 1.2 103 www.national.com Figure 24. Standard Latched Address Mode - X-Bus Write Access Cycle Turbo Read Transactions. A Turbo read cycle starts by outputting the lower 12 address signals on address signals XA11-0 and by outputting address lines 27-20 on data signals XD7-0 on the rising edge of the clock. One CLK cycle later, a strobe signal (XSTB2) is asserted to latch the address in an external latch. One CLK cycle after that, a second set of address lines (19-12) is placed on data pins XD7-0. These can be latched by the strobe signal XSTB1, asserted one cycle later on the rising edge of the clock. One CLK cycle later, the last group of address lines (11-4) is placed on data signals XD7-0. The XSTB0, asserted one cycle later on the rising edge of the clock, can be used to latch this part of the address. One CLK cycle later on the rising edge of the clock, the PC8741x stops driving the data bus. At this point, all addresses are available either at the address outputs of the PC8741x (XA11-0) or in the three latches. The system may require only part of these address- es, depending on the size of the memory or peripheral address space. One CLK cycle later, the chip-select signal XCSn is asserted, based on the XCSn Turbo mode setting. From this point, the read continues as described for the Normal Address Turbo transaction, Mode 0. XSTB2-0 are de-asserted one CLK cycle after the de-assertion of XCSn. At this time, the latched address becomes invalid. At the same time, the address signals XA11-0 are driven to low level. CLK (Internal; for XD7-0 XA27-0 XA11-0 XCSn XWR_XRW (After Latching) [27-20] A [19-12] A XRD_XEN XRDY XSTB2 XSTB1 [11-4] A XSTB0 (Availability on Device Pins Depends on Multiplexing) Transaction Continues as for Non-Latched Address Mode 0 and Mode 1 Write for mode 0 Starting point for mode 1 Starting point [7-0] D Reference Only) |
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