PC87413 datasheet(102/257 Pages) NSC

102 / 257 page

5.0 X-Bus Extension (Continued)

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102

Revision1.2

Figure 23. Standard Latched Address Mode - X-Bus Read Access Cycle

Standard Write Transactions. When a write cycle on the LPC falls within any of the enabled decoded address ranges of

the X-Bus functional block (or an indirect write is started or an X-Bus write through the ACCESS.bus is started), a write cycle

begins. A write cycle starts by outputting the lower 12 address signals on address signals XA11-0 and address lines 27-20

on data signals XD7-0 on the rising edge of the clock. Two CLK cycles later, a strobe signal (XSTB2) is asserted to latch the

address in an external latch. Two CLK cycles after that, a second set of address lines (19-12) is placed on data pins XD7-0.

These can be latched by the strobe signal XSTB1 asserted two cycles later on the rising edge of the clock. Two CLK cycles

later, the last group of address lines (11-4) is output on the data signals XD7-0. The XSTB0, asserted two CLK cycles later

on the rising edge of the clock, can be used to latch this part of the address. Two CLK cycles later on the rising edge of the

clock, the PC8741x outputs the data signals on data pins XD7-0. At this point, all the addresses are available either at the

address outputs of the PC8741x (XA11-0) or at the outputs of the three latches. The system may require only part of these

addresses, depending on the size of the memory or peripheral address space. One CLK cycle later, either a chip-select sig-

nal XCSn or the enable signal XRD_XEN is asserted, based on the XCSn mode setting (where n is a chip-select number

from 0 to 3, based on the address accessed and the select signal mapping). From this point, the write continues as described

for the Normal Address mode. XSTB2-0 are de-asserted one CLK cycle after the de-assertion of XCSn. At this time, the

latched address becomes invalid.

CLK

(Internal; for

XD7-0

XA27-0

XA11-0

XCSn

XWR_XRW

(After Latching)

[27-20]

[19-12]

XRD_XEN

XRDY

XSTB2

XSTB1

[11-4]

XSTB0

(Availability on Device Pins

Depends on Multiplexing)

Transaction Continues as for Non-Latched Address Mode 0 and Mode 1 Read

for mode 0

Starting point

for mode 1

Starting point

Reference Only)

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