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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87413 датащи(PDF) 108 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 108 Page - National Semiconductor (TI) |
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108 / 257 page  5.0 X-Bus Extension (Continued) www.national.com 108 Revision1.2 5.4.2 X-Bus Configuration Register (XBCNF) This register affects the functionality mode of the X-Bus. Power Well:VSB Location:Offset 00h Type: R/W or RO 5.4.3 X-Bus Select Configuration Registers (XZCNF0 to XZCNF3) These registers control the mapping of I/O and Memory Zones to XCSn, where n is from 0 to 3. Power Well:VSB Location:Offset 01h (XZCNF0) Location:Offset 02h (XZCNF1) Location:Offset 0Dh (XZCNF2) Location:Offset 0Eh (XZCNF3) Type: R/W or RO Bit 76543210 Name TBXCS3 TBXCS2 TBXCS1 TBXCS0 Reserved LADEN Reset 0000000 Strap Bit Description 7 TBXCS3 (Turbo Transactions on XCS3). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM3 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 99) when XCS3 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 101), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 6 TBXCS2 (Turbo Transactions on XCS2). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM2 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 99) when XCS2 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 101), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 5 TBXCS1 (Turbo Transactions on XCS1). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM1 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 99) when XCS1 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 101), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 4 TBXCS0 (Turbo Transactions on XCS0). When set to 1 and mode 0 is selected (TRANSMD = 0 in the XZM0 register), enables Turbo X-Bus transactions (see Section 5.2.7 on page 99) when XCS0 is accessed. The Turbo transactions are Normal Address or Latched Address (see Section 5.2.9 on page 101), according to the setting of the LADEN bit. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default) 1: Enabled 3-1 Reserved. 0 LADEN (Latch Address Mode Enabled). When set to 1, enables addresses XA27-XA4 to be multiplexed with the data pins in three phases. Reset value of this bit is set according to the XCNF2 strap, sampled at VSB Power-Up reset. See Section 1.4.11 on page 29 for the definition of strap setting. This bit is locked by setting at least one of the LOCKXSCF bits in the XZM0-XZM3 registers. 0: Disabled (default if XCNF2 = 0 - No BIOS) 1: Enabled (default if XCNF2 = 1 - With BIOS) |
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