PC87413 datasheet(199/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

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9.3.29

Power Active Timers Control Register (PWTMRCTL)

This register controls the reset by software of the VDD and VSB Active Timers. It is reset by hardware to 00h.

Power Well:VPP

Location: Bank 1, Offset 18h

Type:

Varies per bit

9.3.30

S0 to S5 Sleep Type Encoding Registers (S0_SLP_TYP to S5_SLP_TYP)

These registers hold the system Sleep Type encoding for each sleep state: Working (G0/S0), Sleeping (G1/S1-S4) and

Soft-off (G2/S5). The Sleep Type is deﬁned by the SLP_TYPx ﬁeld of the PM1b_CNT_HIGH register (see Section 9.4.7

on page 208). These registers are reset by hardware to 00h.

Power Well:VPP

Location: Bank 2, Offset 10h to 15h

Type:

R/W or RO

Bit

43210

Name

LOCK

_TMRRST

Reserved

VSB_TMR

_RST

Reserved

VDD_TMR

_RST

Reset

00000

Bit

Type

Description

R/W1S LOCK_TMRRST (Lock Timers Reset). When set to 1, this bit locks the VSB_TMR_RST and

VDD_TMR_RST bits by disabling the writing to them (including to the LOCK_TMRRST bit itself). Once

set, this bit can be cleared either by VDD Power-Up reset (or Hardware reset) or by VSB Power-Up

reset, according to the VSBLOCK bit in the ACBLKCTL register (see Section 6.3.4 on page 128). In

addition, this bit is cleared by setting the UNLOCKS bit in the ACBLKCTL register (PC87413 and

PC87417).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-3

Reserved.

R/W or

VSB_TMR_RST (VSB Active Timer Reset). Writing ‘1’ to this bit resets the VSB Active Timer (the timer

is reset within 1 second following the write). This bit then returns to ‘0’ (read always returns ‘0’).

0: Inactive (default)

1: Reset the VSB Active Timer

Reserved.

R/W or

VDD_TMR_RST (VDD Active Timer Reset). Writing ‘1’ to this bit resets the VDD Active Timer (the timer

is reset within 1 second following the write). This bit then returns to ‘0’ (read always returns ‘0’).

0: Inactive (default)

1: Reset the VDD Active Timer

Bit

43210

Name

Reserved

SLP_TYP_ENC

Reset

00000

Bit

Description

7-3

Reserved.

2-0

SLP_TYP_ENC (Sleep Type Encoding). The value used by the system for the sleep state deﬁned by the

speciﬁc register. This value must always be set after VPP reset (default = 000b). For sleep states not supported

by the system, select an unused value.

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