RM0319 datasheet(246/368 Pages) STMICROELECTRONICS

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Fast infrared port (IRDA)

RM0319

246/368

Doc ID 022640 Rev 3

Fast infrared port (IRDA)

This chapter focuses on FirDA functionality and operation.

For technical details about the programmable registers related to the FirDA, refer to the

FirDA registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

19.1

Overview

SPEAr320S provides a fast IrDA Controller modeled according to the standard of the

infrared data association (IrDA).

It is a programmable infrared controller that acts as an interface between the on-chip AHB

bus and infrared transceiver. This controller is able to perform the modulation and the

demodulation of the infrared signals and the wrapping of the IrDA link access protocol

(IrLAP) frames.

19.2

Main features

●

Supports different standards:

–

IrDA serial infrared physical layer specification (IrPHY), version 1.3

–

IrDA link access protocol (IrLAP), version 1.1

●

Supports different infrared modes and baud rates:

–

Serial infrared (SIR), with rates 9.6 Kbps, 19.2 Kbps, 38.4 Kbps, 57.6 Kbps and

115.2 Kbps

–

Medium infrared (MIR), with rates 576 Kbps and 1.152 Mbps

–

Fast infrared (FIR), with rate 4 Mbps.

●

Provides a transceiver interface compliant to all IrDA transceivers with configurable

polarity of TX and RX signals.

●

Integrates half-duplex infrared frame transmission and reception.

●

Integrates 16 bit CRC algorithm for SIR and MIR, and 32 bit CRC algorithm for FIR.

●

Generates preamble, start and stop flag.

●

Uses the RZI (return-to-zero inverted) modulation/demodulation scheme for SIR and

MIR, and the 4PPM (4 pulse position modulation) modulation/demodulation scheme for

FIR.

●

Provides synchronization by means of a DPLL in FIR mode.

●

Implements a payload data transfer controllable by either CPU or DMA controller.

●

Presents two clock domains:

–

a dedicated clock (irda_clk signal) for an accurate signal generation (48 MHz, see

for more details the Miscellaneous register PRPH_CLK_CFG[bit 6:5] and PLL

programming sequence description.

–

an independent and variable clock for the bus interface (13 MHz).

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