RM0319 datasheet(226/368 Pages) STMICROELECTRONICS

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I2C bus ports (I2C)

RM0319

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Doc ID 022640 Rev 3

17.3

Functional description

Figure 81 shows the functional block diagram of the I2C controller.

Figure 81.

I2C controller functional block diagram

17.3.1

APB interface

The host processor accesses data, control and status information on the I2C controller

through the APB Slave Interface. The I2C controller has 16 bit APB data bus width.

17.3.2

I2C protocols

According to the I2C-bus specification, the I2C controller implements the following protocols:

●

START and STOP Condition Protocol,

●

Addressing Slave Protocol,

●

Transmitting and Receiving Protocol,

●

START Byte Transfer Protocol.

START and STOP condition protocol

When the bus is IDLE, both the SCL (serial clock) and SDA (serial data) signals are pulled

high through external pull-up resistors on the bus.

When the I2C master wants to start a transmission on the bus, it issues a START condition

which is defined as a high-to-low transition of the SDA signal while SCL is high (see

Figure 82).

When the I2C master wants to terminate the transmission, it issues a STOP condition which

is defined as a low-to-high transition of the SDA signal while SCL is high.

When data is being transmitted on the bus, the SDA line must be stable when SCL is high.

I2C Debug

APB Slave

Interface

I2C Master/

Slave

Interrupts

RX Filter

Clock

Generator

DMA

Interface

TX -FIFO

RX -FIFO

I2C Controller

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