FXOS8700CQ datasheet(17/86 Pages) FREESCALE

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Freescale Semiconductor, Inc.

5.2.2

SPI READ/WRITE operations

A READ operation is initiated by transmitting a 0 for the R/W bit. Then the 8-bit register address, ADDR[7:0] is encoded in the

first and second serialized bytes. Subsequent bits are ignored by the part. The read data is deserialized from the MISO pin.

Similarly a WRITE operation is initiated by transmitting a 1 for the R/W bit. After the first and second serialized bytes multiple data

bytes can be transmitted into consecutive registers, starting from the indicated register address in ADDR[7:0].

An SPI transaction is started by asserting the CS_B pin (high-to-low transition), and ended by deasserting the CS_B pin (low-to-

high transition).

* Data bytes must be transmitted to the slave (FXOS8700CQ) via MOSI pin by the master when R/W = 1. Data bytes will be transmitted by the

slave (FXOS8700CQ) to the master via MISO pin when R/W = 0. The first 2 bytes are always transmitted by the master via MOSI pin. i.e. a

transaction is always initiated by master.

Figure 8. SPI single-burst READ/WRITE transaction diagram

The registers embedded inside the FXOS8700CQ are accessed through either an I2C, or a SPI serial interface. To enable either

interface the VDDIO line must be connected to the interface supply voltage. If VDD is not present and VDDIO is present

FXOS8700CQ is in shutdown mode and communications on the interface are ignored. If VDDIO is held high, VDD can be

powered off and the communications pins will be in a high impedance state. This will allow communications to continue on the

bus with other devices.

5.2.3

I2C/SPI auto detection

It is possible to factory-trim parts such that the part always uses either I2C or SPI communication protocol. When this trim is not

in place the device will operate in either I2C or SPI interface mode based on the state of the SA0 pin during power up or when

exiting reset. Once set for I2C or SPI operation the device will remain in I2C or SPI mode until the device is reset.

5.2.4

Power supply sequencing and I2C/SPI mode auto detection

This component does not have any specific power supply sequencing requirements between VDD and VDDIO voltage supplies

to ensure normal operation. To ensure correct operation of the I2C/SPI auto-detection function, VDDIO should be applied before

or at the same time as VDD. If this order cannot be maintained, the user should either toggle the RST line or power cycle the

VDD rail in order to force the auto-detect function to restart and correctly identify the desired interface. Please consult the factory

for further options if necessary.

R/W bit followed by ADDR [6:0] ADDR[7] followed by 7 “don’t care” bits

Data0*

Data1

—

Datan

Table 11. Serial interface pin descriptions

Pin Name

Pin Description

VDDIO

Digital interface power

SA1/CS_B

I2C second least significant bit of device address/SPI chip select

SCL/SCLK

I2C/SPI serial clock

SDA/MOSI

I2C serial data/SPI master serial data out slave serial data in

SA0/MISO

I2C least significant bit of the device address/SPI master serial data in slave out

Table 12. I2C/SPI auto detection

SA0

Slave address

GND

I2C

VDDIO

I2C

Floating

SPI

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