FXOS8700CQ datasheet(72/86 Pages) FREESCALE

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Sensors

Freescale Semiconductor, Inc.

9.16.4

M_THS_COUNT (0x5A) register

This register sets the number of debounce sample counts required before a magnetic threshold event is triggered.The behavior

of the debounce counter is controlled by M_THS_X_MSB [m_ths_dbcntm].

When the internal debounce counter reaches the M_THS_COUNT value a magnetic event flag is set. The debounce counter will

never increase beyond the M_THS_COUNT value. The time step used for the debounce sample count depends on the chosen

ODR. When hybrid mode is enabled, the effective ODR is reduced by a factor of two, which increases the debounce counter time

step by a factor of two from what is shown in Table 91.

For example, an ODR of 100 Hz and a M_THS_COUNT value of 15 would result in a debounce response time of 150 ms. In

hybrid mode, the same settings would result in a debounce response time of 300 ms.

m_ths_z[7:0]

0b00000000

Figure 120. M_THS_Z_LSB register

m_ths_cnt[7:0]

0b00000000

Figure 121. M_THS_COUNT register

Table 91. M_THS_COUNT bit description

Field

Description

m_ths_cnt[7:0]

Magnetic threshold debounce count value.

Table 92. M_THS_COUNT relationship with the ODR This table needs to be re-done for this function. Ask design during review

ODR (Hz)

Max time range (s)

Time step (ms)

Normal

LPLN

High

resolution

Low power

Normal

LPLN

High resolution

Low power

800

N/A

400

N/A

0.638

N/A

2.5

200

1.28

N/A

1.28

N/A

100

2.55

N/A

2.55

N/A

5.1

N/A

5.1

N/A

12.5

5.1

20.4

N/A

20.4

N/A

6.25

5.1

40.8

N/A

40.8

160

N/A

160

1.56

5.1

163

N/A

163

640

N/A

640

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