FXOS8700CQ datasheet(16/86 Pages) FREESCALE

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5.2

SPI Interface characteristics

SPI interface is a classical master/slave serial port. The FXOS8700CQ is always considered as the slave and thus is never

initiating the communication.

Table 10 and Figure 7 describe the timing requirements for the SPI system.

Figure 7. SPI Timing Diagram

5.2.1

General SPI operation

The CS_B pin is driven low at the start of a SPI transaction, held low for the duration of the transaction, and driven high after the

transaction is complete. During a transaction the master toggles the SPI clock (SCLK) and transmits data on the MOSI pin.

A write operation is initiated by transmitting a 1 for the R/W bit. Then the 8-bit register address, ADDR[7:0] is encoded in the first

and second serialized bytes. Data to be written starts in the third serialized byte. The order of the bits is as follows:

R/W,ADDR[6],ADDR[5],ADDR[4],ADDR[3],ADDR[2],ADDR[1],ADDR[0],

ADDR[7],X,X,X,X,X,X,X,

DATA[7],DATA[6],DATA[5],DATA[4],DATA[3],DATA[2],DATA[1],DATA[0].

Multiple bytes of DATA may be transmitted. The X indicates a bit that is ignored by the part. The register address is auto-

incremented so that the next clock edges will latch the data for the next register. When desired, the rising edge on CS_B stops

the SPI communication.

The FXOS8700CQ SPI configuration is as follows:

•

Polarity: rising/falling

•

Phase: sample/setup

•

Order: MSB first

Table 10. SPI timing

Function

Symbol

Min

Max

Unit

Operating Frequency

—

MHz

SCLK Period

tSCLK

1000

—

SCLK High time

tCLKH

500

—

SCLK Low time

tCLKL

500

—

CS_B lead time

tSCS

—

CS_B lag time

tHCS

—

MOSI data setup time

tSET

—

MOSI data hold time

tHOLD

—

MISO data valid (after SCLK low edge)

tDDLY

—

500

Width CS High

tWCS

TBD

—

CS_B

SCLK

MOSI

MISO

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