FXOS8700CQ datasheet(32/86 Pages) FREESCALE

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Sensors

Freescale Semiconductor, Inc.

The active bit selects between Standby mode and Active mode. The default value is 0 (Standby mode) on reset.

The lnoise bit selects between normal full dynamic range mode and a high sensitivity, low-noise mode. In low-noise mode the

maximum signal that can be measured is ±4g. Note: Any thresholds set above 4g will not be reached.

The f_read bit selects between normal and fast-read modes where the auto-increment counter will also skip over the LSB data

bytes when f_read = 1. Data read from the FIFO will also skip over the LSB data, reducing the data acquisition time. In hybrid

mode and with M_CTRL_REG2[hyb_autoinc_mode] = 1, all of the sensor data MSB's can be read out with a single 6-byte burst

read starting at the OUT_X_MSB register. Note: The f_read bit can only be changed while F_SETUP[f_mode] = 0

9.1.9

CTRL_REG2 (0x2B) register

Table 24. System Output Data Rate selection

dr2

dr1

dr0

ODR accelerometer or

magnetometer only modes

(Hz)

Period accelerometer or

magnetometer only modes

(ms)

ODR hybrid mode (Hz)

Period hybrid mode (ms)

800.0

1.25

400

2.5

400.0

2.5

200

200.0

100

100.0

50.0

202580

12.5

6.25

160

6.3

160

3.15

320

1.6

640

0.8

1280

rst

—

smods[1:0]

slpe

mods[1:0]

000000

Figure 18. CTRL_REG2 register

Table 25. CTRL_REG2 bit descriptions

Field

Description

The st bit activates the accelerometer self-test function. When st is set to 1, an output change will occur to the device outputs

thus allowing the host application to check the functionality of the entire measurement signal chain.

Self-Test Enable:

0: Self-Test disabled

1: Self-Test enabled.

rst

The rst bit is used to initiate a software reset. The reset mechanism can be enabled in both Standby and Active modes. When

the rst bit is set, the boot mechanism resets all functional block registers and loads the respective internal registers with their

default values. After setting the rst bit, the system will automatically transition to Standby mode. Therefore, if the system was

already in Standby mode, the reboot process will immediately begin; else if the system was in Active mode the boot mechanism

will automatically transition the system from Active mode to Standby mode, only then can the reboot process begin. A system

reset can also be initiated by pulsing the external RST pin high

The I2C and SPI communication systems are also reset to avoid corrupted data transactions. The host application should allow

1 ms between issuing a software (setting rst bit) or hardware (pulsing RST pin) reset and attempting communications with the

device over the I2C or SPI interfaces.

At the end of the boot process the rst bit is deasserted to 0. Reading this bit will always return a value of 0.

0: Device reset disabled

1: Device reset enabled.

smods[1:0]

Sleep mode power scheme selection. See Table 25 for more information.

slpe(1)

1. When SLPE = 1, a transition between Sleep mode and Wake mode results in a FIFO flush and a reset of internal functional block counters.

All functional block status information is preserved except where otherwise stated. For further information, refer to the CRTL_REG3 register

description (FIFO_GATE bit).

Auto-Sleep mode enable:

0: Auto-Sleep is not enabled

1: Auto-Sleep is enabled.

mods[1:0]

Accelerometer OSR selection. This setting, along with the ODR selection determines the Active mode power and RMS noise

for acceleration measurements.

See Table 25 for more information.

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