FXOS8700CQ datasheet(53/86 Pages) FREESCALE

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Sensors

Freescale Semiconductor, Inc.

9.10.3

A_VECM_THS_LSB (0x61) register

9.10.4

A_VECM_CNT (0x62) register

The debounce timer period is determined by the ODR selected in CTRL_REG1. For example, in accelerometer only mode with

an ODR of 100 Hz and a_vecm_cnt = 15, the debounce time is set at 150 ms. When operating in hybrid mode, the effective ODR

is reduced by a factor of two, making the debounce time 300 ms for this example.

Table 56. A_VECM_THS_MSB bit descriptions

Field

Description

a_vecm_dbcntm

Control bit a_vecm_dbcntm defines how the debounce timer is reset when the condition for triggering the interrupt is

no longer true.

When a_vecm_dbcntm = 0 the debounce counter is decremented by 1 when the vector magnitude result is below the

programmed threshold value.

When a_vecm_dbcntm = 1 the debounce counter is cleared when the vector magnitude result is below the

programmed threshold value.

a_vecm_ths[12:8]

Five MSBs of the 13-bit unsigned A_VECM_THS value. The resolution is equal to the selected accelerometer

resolution set in XYZ_DATA_CFG[fs]

a_vecm_ths[7:0]

0b00000000

Figure 58. A_VECM_THS_LSB register

a_vecm_cnt[7:0]

0b00000000

Figure 59. A_VECM_CNT register

Table 57. A_VECM_CNT bit description

Field

Description

a_vecm_cnt[7:0]

Vector magnitude function debounce count value.

Table 58. A_VECM_CNT relationship with selected ODR and power mode

ODR (Hz)

Max time range (s)

Time Step (ms)

Normal

LPLN

High

resolution

Low power

Normal

LPLN

High

resolution

Low power

800

0.318

1.25

400

0.318

0.638

1.25

2.5

200

0.638

0.318

1.276

2.5

1.25

100

1.276

0.318

2.56

1.25

2.56

0.318

5.1

1.25

12.5

2.56

10.2

0.318

20.4

1.25

6.25

2.56

20.4

0.318

40.8

1.25

160

1.56

2.56

81.6

0.318

163.2

320

1.25

640

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