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FXOS8700CQ датащи(PDF) 37 Page - Freescale Semiconductor, Inc |
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FXOS8700CQ датащи(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 86 page ![]() Sensors Freescale Semiconductor, Inc. 37 Please note that when the device is operated in hybrid mode, the effective ODR is half of what is selected in CTRL_REG1[dr]. For example, with ODR = 800 Hz and the device set to hybrid mode, the ASLP_COUNT time step becomes 640 ms. * If the FIFO_GATE bit is set to logic ‘1’, the assertion of the SRC_ASLP interrupt does not prevent the system from transitioning to Sleep or from Wake mode; instead it prevents the FIFO buffer from accepting new sample data until the host application flushes the FIFO buffer. The interrupt sources listed in Table 33 affect the auto-sleep, return to sleep and wake from sleep mechanism only if they have been previously enabled. The functional block event flags that are bypassed while the system is in Auto-Sleep mode are temporary disabled (see CTRL_REG3 register for more information) and are automatically re-enabled when the device returns from Auto-Sleep mode (i.e. wakes up), except for the data ready function. If any of the interrupt sources listed under the Return-to-Sleep column is asserted before the sleep counter reaches the value specified in ASLP_COUNT, then all sleep mode transitions are terminated and the internal sleep counter is reset. If none of the interrupts listed under the Return-to-Sleep column are asserted within the time limit specified by the ASLP_COUNT register, the system will transition to the Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate]. aslp_cnt[7:0] 0b00000000 Figure 24. ASLP_COUNT register Table 31. ASLP_COUNT bit description Field Description aslp_cnt[7:0] See Table 31 for details Table 32. ASLP_COUNT relationship with ODR Output Data Rate (ODR) Duration (s) ODR time step (ms) ASLP_COUNT step (ms) 800 0 to 81 1.25 320 400 0 to 81 2.5 320 200 0 to 81 5 320 100 0 to 81 10 320 50 0 to 81 20 320 12.5 0 to 81 80 320 6.25 0 to 81 160 320 1.56 0 to 163 640 640 Table 33. Sleep/Wake mode gates and triggers Interrupt source Event restarts time and delays Return-to-Sleep Event will Wake-from-Sleep SRC_FIFO Yes No SRC_TRANS Yes Yes SRC_LNDPRT Yes Yes SRC_PULSE Yes Yes SRC_FFMT Yes Yes SRC_ASLP No* No* SRC_Mag Yes Yes SRC_DRDY No No SRC_AVECM Yes Yes SRC_MVECM Yes Yes SRC_MTHS Yes Yes |
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