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FXOS8700CQ датащи(PDF) 61 Page - Freescale Semiconductor, Inc |
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FXOS8700CQ датащи(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 86 page ![]() Sensors Freescale Semiconductor, Inc. 61 Therefore an ODR setting of 400 Hz with normal power mode would result in a maximum pulse time limit of (0.625 ms * 255) ≥ 159 ms. 9.12.7 PULSE_LTCY (0x27) register Minimum time step for the pulse latency is defined in Tables 78 and 79. Maximum time is “(time step @ ODR and power mode) x 255”. 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 40.8 0.638 40.8 20 160 2.5 160 1.56 5.1 163 0.638 163 20 640 2.5 640 Table 77. Time step for PULSE time limit LPF_EN = 0 ODR (Hz) Max time range (s) Time step (ms) Normal LPLN High resolution Low power Normal LPLN High resolution Low power 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.2 5 20 0.625 40 6.25 1.28 10.2 0.159 20.4 5 40 0.625 80 1.56 1.28 40.8 0.159 81.6 5 160 0.625 320 pls_ltcy[7:0] 0b00000000 Figure 76. PULSE_LTCY register Table 78. PULSE_LTCY bit description Field Description pls_ltcy[7:0] pls_ltcy[7:0] defines the time interval that starts after the first pulse detection where the pulse detection function ignores the start of a new pulse. Table 79. Time step for PULSE latency @ ODR and power mode LPF_EN = 1 ODR (Hz) Max time range (s) Time step (ms) Normal LPLN High resolution Low power Normal LPLN High resolution Low power 800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 400 1.276 1.276 1.276 1.276 5 5 5 5 200 2.56 2.56 1.276 2.56 10 10 5 10 100 5.1 5.1 1.276 5.1 20 20 5 20 50 10.2 10.2 1.276 10.2 40 40 5 40 12.5 10.2 40.8 1.276 40.8 40 160 5 160 6.25 10.2 81.6 1.276 81.6 40 320 5 320 1.56 10.2 326 1.276 326 40 1280 5 1280 Table 76. Time step for pulse time limit LPF_EN = 1 |
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