FXOS8700CQ datasheet(57/86 Pages) FREESCALE

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Freescale Semiconductor, Inc.

When TRANSIENT_CFG[tran_ele] = 1, the TRANSIENT_SRC event flag(s) and polarity bits are latched when the interrupt event

is triggered, allowing the host application to determine which event flag(s) originally triggered the interrupt. When

TRANSIENT_CFG[tran_ele] = 0, events which occur after the event that originally triggered the interrupt will update the flag and

polarity bits, but once set, the flags can only be cleared by reading the TRANSIENT_SRC register.

9.11.3

TRANSIENT_THS (0x1F) register

The TRANSIENT_THS register determines the debounce counter behavior and also sets the transient event detection

threshold.It is possible to use A_FFMT_THS_X/Y/Z MSB and LSB registers to set transient acceleration thresholds for individual

axes via a_ffmt_trans_ths_en bit in A_FFMT_THS_Y_MSB register. Please see Section 9.9.3 for more details.

The tr_ths[6:0] value is a 7-bit unsigned number, with a fixed resolution of 63 mg/LSB corresponding to a ±8g measurement

range. The resolution does not change with the full-scale range setting made in XYZ_DATA_CFG[fs]. If CTRL_REG1[lnoise] = 1,

the measurement range is fixed at ±4g, regardless of the settings made in XYZ_DATA_CFG.

9.11.4

TRANSIENT_COUNT (0x20) register

The TRANSIENT_COUNT register sets the minimum number of debounce counts needed to trigger the transient event interrupt

flag when the measured acceleration value exceeds the threshold set in TRANSIENT_THS for any of the enabled axes.

The time step for the transient detection debounce counter is set by the value of the system ODR and power mode as shown in

Table 68. When the device is operated in hybrid mode, the effective ODR is half of what is selected in CTRL_REG1, which also

doubles the time-step values shown in Table 68.

tr_dbcntm

tr_ths[6:0]

0b0000000

Figure 68. TRANSIENT_THS register

Table 67. TRANSIENT_THS bit descriptions

Field

Description

tr_dbcntm

Debounce counter mode selection.

0: Decrements debounce counter when the transient event condition is not true during the current ODR period.

1: Clears debounce counter when the transient event condition is not true during the current ODR period.

tr_ths[6:0]

Transient event threshold. This register has a resolution of 63mg/LSB regardless of the full-scale range setting made in

XYZ_DATA_CFG[fs]. If CTRL_REG1[lnoise] = 1, the maximum acceleration measurement range is ±4g.

tr_count[7:0]

0b00000000

Figure 69. TRANSIENT_COUNT register

Table 68. TRANSIENT_COUNT bit description

Field

Description

tr_count[7:0)

Transient function debounce count value.

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