FXOS8700CQ datasheet(36/86 Pages) FREESCALE

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Freescale Semiconductor, Inc.

Figure 22. Interrupt controller block diagram

The system’s interrupt controller uses the corresponding bit field in the CTRL_REG5 register to determine the routing for the INT1

and INT2 interrupt pins. For example, if the int_cfg_drdy bit value is logic ‘0’ the functional block’s interrupt is routed to INT2, and

if the bit value is logic ‘1’ then the interrupt is routed to INT1. All interrupt signals routed to either INT1 or INT2 are logically ored

together as illustrated in Figure 23, thus one or more functional blocks can assert an interrupt pin simultaneously; therefore a

host application responding to an interrupt should read the INT_SOURCE register to determine the appropriate sources of the

interrupt(s).

Figure 23. INT1/INT2 PIN Control Logic

9.2

Auto-Sleep trigger

9.2.1

ASLP_COUNT (0x29) register

The ASLP_COUNT register sets the minimum time period of event flag inactivity required to initiate a change from the current

active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate],

provided that CTRL_REG2[slpe] = 1.

See Table 32 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event.

INTERRUPT

CONTROLLER

Data Ready

Freefall/Motion Detection

Pulse Detection

Orientation Detection

Transient Acceleration Detection

Auto-Sleep

INT ENABLE

INT CFG

INT1

INT2

Acceleration Vector Magnitude

Magnetic Vector Magnitude

Magnetic Threshold Detection

FIFO Interrupt

INT1

INT2

SRC_RTS

SRC_FIFO

SRC_PULSE

SRC_FF_MT

SRC_DRDY

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