FXOS8700CQ datasheet(60/86 Pages) FREESCALE

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Freescale Semiconductor, Inc.

corresponding to an 8g acceleration full-scale range. The full-scale range is fixed at 8g for the pulse detection function, regardless

of the settings made in XYZ_DATA_CFG[fs].

9.12.4

PULSE_THSY (0x24) register

9.12.5

PULSE_THSZ (0x25) register

9.12.6

PULSE_TMLT (0x26) register

Minimum time step for the pulse time limit is defined in Tables 75 and 76. Maximum time for a given ODR is “Minimum time step

x 255”.

—

pls_thsy[6:0]

0b0000000

Figure 73. PULSE_THSY register

Table 73. PULSE_THSY bit description

Field

Description

pls_thsy[6:0]

Pulse threshold for Y-axis.

—

pls_thsz[6:0]

0b0000000

Figure 74. PULSE_THSZ register

Table 74. PULSE_THSZ bit description

Field

Description

pls_thsz[6:0]

Pulse threshold for Z-axis.

pls_tmlt[7:0]

0b00000000

Figure 75. PULSE_TMLT register

Table 75. PULSE_TMLT bit description

Field

Description

pls_tmlt[7:0]

pls_tmlt[7:0] defines the maximum time interval that can elapse between the start of the acceleration on the selected

channel exceeding the specified threshold and the end when the channel acceleration goes back below the specified

threshold.

Table 76. Time step for pulse time limit LPF_EN = 1

ODR (Hz)

Max time range (s)

Time step (ms)

Normal

LPLN

High

resolution

Low power

Normal

LPLN

High

resolution

Low power

800

0.319

1.25

400

0.638

2.5

200

1.28

0.638

1.28

2.5

100

2.55

0.638

2.55

2.5

5.1

0.638

5.1

2.5

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