FXOS8700CQ datasheet(44/86 Pages) FREESCALE

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Sensors

Freescale Semiconductor, Inc.

9.8.2

PL_CFG (0x11) register

This register enables the Portrait/Landscape function and sets the behavior of the debounce counter.

9.8.3

PL_COUNT (0x12) register

This register sets the debounce count for the orientation state transition. The minimum debounce latency is determined by the

system ODR value and the value of the PL_COUNT register. Any change to the system ODR or a transition from Active to

Standby (or vice-versa) resets the internal landscape/portrait internal debounce counters. When the device is operated in hybrid

mode, the effective ODR will be half of what is selected by the user, which will also affect the debounce time. For example, if an

ODR of 400 Hz is selected and the part is also in hybrid mode, the effective ODR is 200 HZ, and the effective debounce time

step is 5 ms instead of 2.5 ms

9.8.4

PL_BF_ZCOMP (0x13) register

Back/Front and Z-tilt angle compensation register

dbcntm

pl_en

—————

—

10000011

Figure 40. PL_CFG register

Table 40. PL_CFG bit descriptions

Field

Description

dbcntm

Debounce counter mode selection.

0: Decrements debounce whenever condition of interest is no longer valid.

1: Clears counter whenever condition of interest is no longer valid.

pl_en

Portrait/Landscape detection enable.

0: Portrait/Landscape detection is disabled.

1: Portrait/Landscape detection is enabled.

dbnce[7:0]

Figure 41. PL_COUNT register

Table 41. PL_Count Relationship with the ODR

ODR (Hz)

Max time range (s)

Time step (ms)

Normal

LPLN

High

resolution

Low power

Normal

LPLN

High

resolution

Low power

800

0.319

1.25

400

0.638

2.5

200

1.28

0.638

1.28

2.5

100

2.55

0.638

2.55

2.5

5.1

0.638

5.1

2.5

12.5

5.1

20.4

0.638

20.4

2.5

6.25

5.1

40.8

0.638

40.8

160

2.5

160

1.56

5.1

163

0.638

163

640

2.5

640

bkfr[1:0]

—

zlock[2:0]

0000

0b010

Figure 42. PL_BF_ZCOMP register

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