PIC18F23K22-ESLASHML datasheet(113/496 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 113

PIC18(L)F2X/4XK22

9.0

INTERRUPTS

The PIC18(L)F2X/4XK22 devices have multiple

interrupt sources and an interrupt priority feature that

allows most interrupt sources to be assigned a high or

low priority level (INT0 does not have a priority bit, it is

always a high priority). The high priority interrupt vector

is at 0008h and the low priority interrupt vector is at

0018h. A high priority interrupt event will interrupt a low

priority interrupt that may be in progress.

There are 19 registers used to control interrupt

operation.

These registers are:

• INTCON, INTCON2, INTCON3

• PIR1, PIR2, PIR3, PIR4, PIR5

• PIE1, PIE2, PIE3, PIE4, PIE5

• IPR1, IPR2, IPR3, IPR4, IPR5

• RCON

It is recommended that the Microchip header files sup-

plied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

In general, interrupt sources have three bits to control

their operation. They are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

9.1

Mid-Range Compatibility

When the IPEN bit is cleared (default state), the interrupt

priority feature is disabled and interrupts are compatible

with PIC® microcontroller mid-range devices. In

Compatibility mode, the interrupt priority bits of the IPRx

registers have no effect. The PEIE/GIEL bit of the

INTCON register is the global interrupt enable for the

peripherals. The PEIE/GIEL bit disables only the

peripheral interrupt sources and enables the peripheral

interrupt sources when the GIE/GIEH bit is also set. The

GIE/GIEH bit of the INTCON register is the global

interrupt enable which enables all non-peripheral

interrupt sources and disables all interrupt sources,

including the peripherals. All interrupts branch to

address 0008h in Compatibility mode.

9.2

Interrupt Priority

The interrupt priority feature is enabled by setting the

IPEN bit of the RCON register. When interrupt priority

is enabled the GIE/GIEH and PEIE/GIEL global inter-

rupt enable bits of Compatibility mode are replaced by

the GIEH high priority, and GIEL low priority, global

interrupt enables. When set, the GIEH bit of the

INTCON register enables all interrupts that have their

associated IPRx register or INTCONx register priority

bit set (high priority). When clear, the GIEH bit disables

all interrupt sources including those selected as low pri-

ority. When clear, the GIEL bit of the INTCON register

disables only the interrupts that have their associated

priority bit cleared (low priority). When set, the GIEL bit

enables the low priority sources when the GIEH bit is

also set.

When the interrupt flag, enable bit and appropriate

Global Interrupt Enable (GIE) bit are all set, the

interrupt will vector immediately to address 0008h for

high priority, or 0018h for low priority, depending on

level of the interrupting source’s priority bit. Individual

interrupts can be disabled through their corresponding

interrupt enable bits.

9.3

Interrupt Response

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. The

GIE/GIEH bit is the global interrupt enable when the

IPEN bit is cleared. When the IPEN bit is set, enabling

interrupt priority levels, the GIEH bit is the high priority

global interrupt enable and the GIEL bit is the low

priority global interrupt enable. High priority interrupt

sources can interrupt a low priority interrupt. Low

priority interrupts are not processed while high priority

interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits in the INTCONx and PIRx

registers. The interrupt flag bits must be cleared by

software before re-enabling interrupts to avoid

repeating the same interrupt.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE/GIEH bit (GIEH

or GIEL if priority levels are used), which re-enables

interrupts.

For external interrupt events, such as the INT pins or

the PORTB interrupt-on-change, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one-cycle or two-cycle

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