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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny43U датащи(PDF) 151 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 151 Page - ATMEL Corporation |
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151 / 182 page  151 8048B–AVR–03/09 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 19.7 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 19-7 below. Figure 19-7. Serial Programming and Verify Note: If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for f ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz Table 19-14. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB4 I Serial Data in MISO PB5 O Serial Data out SCK PB6 I Serial Clock VCC GND SCK MISO MOSI RESET/PA7 +1.8 - 5.5V PB4 PB5 PB6 |
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