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ATtiny43U датащи(PDF) 127 Page - ATMEL Corporation |
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ATtiny43U датащи(HTML) 127 Page - ATMEL Corporation |
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127 / 182 page ![]() 127 8048B–AVR–03/09 • Bits 2:0 – MUX[2:0]: Analog Channel Selection Bits The value of these bits selects which analog input is connected to the ADC, as shown in Table 16-4. Selecting channel ADC4 enables temperature measurement. Notes: 1. Due to the voltage divider present, a current will flow from VBAT to ground via a 100kΩ resistor divider as long as this channel is selected. 2. See “Temperature Measurement” on page 125. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). 16.13.2 ADCSRA – ADC Control and Status Register A • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa- tion of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con- version on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. Table 16-4. ADC Multiplexer Channel Selections. Single Ended Input MUX[2:0] ADC0 (PA0) 000 ADC1 (PA1) 001 ADC2 (PA2) 010 ADC3 (PA3) 011 0V (GND) 100 1.1V (I Ref) 101 V BAT (1) 110 ADC4 (2) 111 Bit 7654 321 0 0x06 (0x26) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 |
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