ATtiny43U datasheet(116/182 Pages) ATMEL

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116

8048B–AVR–03/09

ATtiny43U

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion.

The analog multiplexer allows eight single-ended channels to be connected to the ADC, includ-

ing the low four bits of port A, the internal temperature sensor, the internal voltage reference,

supply voltage (V

BAT) and ground (GND).

Internal reference voltage of nominally 1.1V is provided on-chip. Alternatively, V

CC can be used

as reference voltage.

16.3

ADC Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the reference

voltage.The voltage reference for the ADC may be selected by writing to the REFS bit in

ADMUX. The VCC supply or an internal 1.1V voltage reference may be selected as the ADC

voltage reference.

The analog input channel is selected by writing to the MUX2..0 bits in ADMUX. Any of the four

ADC input pins ADC3..0, and V

BAT input pin can be selected as single ended input to the ADC.

The on-chip temperature sensor is selected by writing “111” to the MUX2..0 bits in the ADMUX

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADCSRB.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

16.4

Starting a Conversion

Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power

Reduction Register, PRR (see “PRR – Power Reduction Register” on page 35).

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS

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