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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX35 датащи(PDF) 109 Page - Freescale Semiconductor, Inc |
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IMX35 датащи(HTML) 109 Page - Freescale Semiconductor, Inc |
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109 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 109 4.9.18 Parallel Interface (ULPI) Timing Electrical and timing specifications of the parallel interface are presented in the subsequent sections. Figure 86. USB Transmit/Receive Waveform in Parallel Mode 4.9.19 PWM Electrical Specifications This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external Table 70. Signal Definitions—Parallel Interface Name Direction Signal Description USB_Clk In Interface clock. All interface signals are synchronous to the clock. USB_Data[7:0] I/O Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir. USB_Dir In Direction. Control the direction of the data bus. USB_Stp Out Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. USB_Nxt In Next. The PHY asserts this signal to throttle the data. Table 71. USB Timing Specification in VP_VM Unidirectional Mode ID Parameter Min. Max. Unit Conditions / Reference Signal US15 USB_TXOE_B — 6.0 ns 10 pF US16 USB_DAT_VP — 0.0 ns 10 pF US17 USB_SE0_VM — 9.0 ns 10 pF USB_Dir/Nxt USB_Stp US17 US16 USB_Data US15 US16 US15 US17 USB_Clk |
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