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IMX35 датащи(PDF) 71 Page - Freescale Semiconductor, Inc

номер детали IMX35
подробное описание детали  i.MX35 Applications Processors for Industrial and Consumer Products
PDF  148 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

IMX35 датащи(HTML) 71 Page - Freescale Semiconductor, Inc

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6
Freescale Semiconductor
71
Figure 51 depicts the synchronous display interface timing for access level, and Table 52 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
IP9
Horizontal blank interval 1
Thbi1
BGXP
× Tdpcp
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH – BGXP – FW)
× Tdpcp
ns
IP11
HSYNC delay
Thsd
H_SYNC_DELAY
× Tdpcp
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT + 1)
× Tsw
ns
IP13
VSYNC width
Tvsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1)
× Tdpcp
else
(V_SYNC_WIDTH + 1)
× Tsw
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP
× Tsw
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT – BGYP – FH)
× Tsw
ns
1 Display interface clock period immediate value
Display interface clock period average value.
Table 51. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
ID
Parameter
Symbol
Value
Units
Tdicp
T
HSP_CLK
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
⋅
=
IP19
DISPB_D3_CLK
DISPB_DATA
IP18
IP20
DISPB_D3_VSYNC
IP17
IP16
DISPB_D3_DRDY
DISPB_D3_HSYNC
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