IMX35 datasheet(57/148 Pages) FREESCALE

57 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

SCKT rising edge to FST out (wr) high5

—

20.0

10.0

x ck

i ck

SCKT rising edge to FST out (wr) low5

—

22.0

12.0

x ck

i ck

SCKT rising edge to FST out (wl) high

—

19.0

9.0

x ck

i ck

SCKT rising edge to FST out (wl) low

—

20.0

10.0

x ck

i ck

SCKT rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

SCKT rising edge to data out valid

—

18.0

13.0

x ck

i ck

SCKT rising edge to data out high impedance 67

—

21.0

16.0

x ck

i ck

FST input (bl, wr) setup time before SCKT falling edge5

—

2.0

18.0

—

x ck

i ck

FST input (wl) setup time before SCKT falling edge

—

2.0

18.0

—

x ck

i ck

FST input hold time after SCKT falling edge

—

4.0

5.0

—

x ck

i ck

1 i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

2 bl = bit length

wl = word length

wr = word length relative

3 SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

6 Periodically sampled and not 100% tested.

Table 42. Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics1,2

Symbol

Expression2

Min.

Max.

Condition3 Unit

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