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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX35 датащи(PDF) 63 Page - Freescale Semiconductor, Inc |
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IMX35 датащи(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 63 Figure 42 shows MII asynchronous input timings listed in Table 46. Figure 42. MII Asynch Inputs Timing Diagram 4.9.8.5 MII Serial Management Channel Timing Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 47 lists MII serial management channel timings. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 47. MII Transmit Signal Timing Num Characteristic Min. Max. Units M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0— ns M11 FEC_MDC falling edge to FEC_MDIO output valid (max. propagation delay) —5 ns M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns M14 FEC_MDC pulse width high 40% 60% FEC_MDC period M15 FEC_MDC pulse width low 40% 60% FEC_MDC period FEC_CRS, FEC_COL M9 |
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