IMX35 datasheet(76/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.13.3.7

Interface to a TV Encoder, Electrical Characteristics

The timing characteristics of the TV encoder interface are identical to the synchronous display

characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical

Characteristics.”

4.9.13.4

Asynchronous Interfaces

This section discusses the asynchronous parallel and serial interfaces.

4.9.13.4.8

Parallel Interfaces, Functional Description

The IPU supports the following asynchronous parallel interfaces:

•

System 80 interface

— Type 1 (sampling with the chip select signal) with and without byte enable signals.

— Type 2 (sampling with the read and write signals) with and without byte enable signals.

•

System 68k interface

— Type 1 (sampling with the chip select signal) with or without byte enable signals.

— Type 2 (sampling with the read and write signals) with or without byte enable signals.

For each of four system interfaces, there are three burst modes:

1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters

of the IDMAC (when data is transferred from the system memory) or by the HBURST signal

(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system

68k type 1 interfaces, data is sampled by the CS signal and other control signals change only when

transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD

signals (system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during

the whole burst.

2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the

DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are

changed simultaneously with data when the bus state (read, write or wait) is altered. The CS

signals and other controls move to non-active state after burst has been completed.

3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The

data is sampled with CS or other controls according to the interface type as described above. All

controls (including CS) become non-active for one display interface clock after each access. This

mode corresponds to the ATI single access mode.

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 54,

Figure 55, Figure 56, and Figure 57. These timing images correspond to active-low DISPB_Dn_CS,

DISPB_Dn_WR and DISPB_Dn_RD signals.

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