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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX35 датащи(PDF) 55 Page - Freescale Semiconductor, Inc |
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IMX35 датащи(HTML) 55 Page - Freescale Semiconductor, Inc |
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55 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 55 NOTE SDRAM CLK and DQS-related parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. Table 40 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. Figure 36. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram NOTE SDRAM CLK and DQS-related parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value, and “low” is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. Table 41 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. Table 41. Mobile DDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). tDQSQ — 0.85 ns SD22 DQS DQ HOLD time from DQS tQH 2.3 — ns SD23 DQS output access time from SDCLK posedge tDQSCK — 6.7 ns SDCLK SDCLK DQS (input) DQ (input) Data Data Data Data Data Data Data Data SD23 SD21 SD22 |
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