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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX35 датащи(PDF) 49 Page - Freescale Semiconductor, Inc |
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IMX35 датащи(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 49 NOTE SDR SDRAM CLK parameters are measured from the 50% point—that is, “high” is defined as 50% of signal value and “low” is defined as 50% of signal value. The timing parameters are similar to the ones used in SDRAM data sheets. Table 34 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. Figure 30. SDRAM Self-Refresh Cycle Timing Diagram SD7 Address hold time tAH 1.8 — ns SD10 Precharge cycle period1 tRP 1 4 clock SD11 Auto precharge command period1 tRC 2 20 clock 1 SD10 and SD11 are determined by SDRAM controller register settings. Table 34. SDRAM Refresh Timing Parameters (continued) ID Parameter Symbol Min. Max. Unit SDCLK CS CAS RAS ADDR BA WE CKE Don’t care SD16 SD16 |
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