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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX35 датащи(PDF) 45 Page - Freescale Semiconductor, Inc |
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IMX35 датащи(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 45 4.9.5.3 ESDCTL Electrical Specifications Figure 27 through Figure 36 depict the timings pertaining to the ESDCTL module, which interfaces with mobile DDR or SDR SDRAM. Table 32 through Table 41 list the timing parameters. Figure 27. SDRAM Read Cycle Timing Diagram Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min. Max. Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.0 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns SD6 Address setup time tAS 2.0 — ns SDCLK WE ADDR DQ DQM COL/BA Data CS CAS RAS Note: CKE is high during the read/write cycle. SD4 SD1 SD3 SD2 SD4 SD4 SD4 SD4 SD5 SD5 SD5 SD5 SD5 SD6 SD7 SD10 SD8 SD9 SDCLK ROW/BA |
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