IMX35 datasheet(100/148 Pages) FREESCALE

100 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

100

The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in

different transfer modes. There are various requirements for timing relationships among the function pins,

in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA

module registers.

4.9.17.1

General Timing Requirements

Table 63 and Figure 75 define the AC characteristics of the interface signals on all data transfer modes.

Figure 75. ATA Interface Signals Timing Diagram

4.9.17.2

ATA Electrical Specifications (ATA Bus, Bus Buffers)

This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.

Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.

The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These

factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use

of bus buffers is not recommended if fast UDMA mode is required.

The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven

on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers

specify the slew rate of the outgoing signals.

When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal

ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When

ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention

on the host and device tri-state buses is always avoided.

Table 63. AC Characteristics of All Interface Signals

Parameter

Symbol

Min.

Max.

Unit

SI1

Rising edge slew rate for any signal on the ATA interface1

1 SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with

all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.

Srise

—1.25

V/ns

SI2

Falling edge slew rate for any signal on the ATA interface1

Sfall

—1.25

V/ns

SI3

Host interface signal capacitance at the host connector

Chost

—20

ATA Interface Signals

SI1

SI2

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