| поискавой системы для электроныых деталей |
|
IMX35 датащи(PDF) 70 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
IMX35 датащи(HTML) 70 Page - Freescale Semiconductor, Inc |
|
70 / 148 page ![]() i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 70 of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals. Figure 49. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 50 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse Table 51 shows timing parameters of signals presented in Figure 49 and Figure 50. Table 51. Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter Symbol Value Units IP5 Display interface clock period Tdicp Tdicp1 ns IP6 Display pixel clock period Tdpcp (DISP3_IF_CLK_CNT_D + 1) × Tdicp ns IP7 Screen width Tsw (SCREEN_WIDTH + 1) × Tdpcp ns IP8 HSYNC width Thsw (H_SYNC_WIDTH + 1) × Tdpcp ns DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA DISPB_D3_CLK IP7 IP9 IP10 IP8 Start of line IP5 IP6 IP14 DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY Start of frame End of frame IP12 IP15 IP13 IP11 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |