IMX35 datasheet(67/148 Pages) FREESCALE

67 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.

4.9.12.2.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 45.

Figure 45. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock

is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,

the SENSB_VSYNC timing repeats.

4.9.12.2.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),

except for the SENSB_HSYNC signal, which is not used. See Figure 46. All incoming pixel clocks are

valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states

low) until valid data is going to be transmitted over the bus.

Figure 46. Non-Gated Clock Mode Timing Diagram

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[9:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Active Line

Start of Frame

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[7:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

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