M16CSLASH1N datasheet(219/238 Pages) RENESAS

219 / 238 page

Rev.1.00

Oct 20, 2004

page 207 of 222

M16C/1N Group

REJ090007-0100Z

20. Precautionary Notes in Using the Device

20.2 Interrupts

20.2.1 Reading Address 0000016

Do not read the address 0000016 in a program. When a maskable interrupt request is accepted,

the CPU reads interrupt information (interrupt number and interrupt request priority level) from the

address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is

cleared to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the

highest priority among the enabled interrupts is cleared to "0". This causes a problem that the

interrupt is canceled, or an unexpected interrupt is generated.

20.2.2 Stack Pointer

Set the value of the stack pointer before accepting interrupts. Immediately after a reset, the value

of the stack pointer is 000016. Accepting an interrupt before setting a value of the stack pointer

may produce unpredictable results (runaway program, etc.) Make sure that you set the value of

the stack pointer before accepting interrupts.

20.2.3 External interrupts

________

Clear the interrupt request bit to "0" when the INT0 to INT3 pins and CNTR0 pin polarity are

changed. The reason being is that an interrupt request may be generated when the polarity is

changed.

20.2.4 Rewriting the Interrupt Control Register

When rewriting the Interrupt Control Register, do it at a point where it does not generate an inter-

rupt request for that register. If there is a possibility that an interrupt may occur, disable the inter-

rupt before rewriting. Examples are shown below.

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00H, 0055H

; Clear T1IC int. priority level and int. request bit.

NOP

;

NOP

FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00H, 0055H

; Clear T1IC int. priority level and int. request bit.

MOV.W

MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC

FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00H, 0055H

; Clear T1IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

Note 1: The reason why two NOP instructions or dummy read were inserted before the FSET I for

ex. 1 & 2 is to prevent interrupt enable flag from being set, due to the effects of instruction

queue, before the rewritten value of the interrupt control register takes effect.

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