M16CSLASH1N datasheet(209/238 Pages) RENESAS

209 / 238 page

Rev.1.00

Oct 20, 2004

page 197 of 222

M16C/1N Group

19. Flash Memory Version

REJ09B0007-0100Z

Description

Name

I/O

Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to

Vss pin.

Connect a capacitor (0.1

µF) to VSS pin.

Connect to VCC pin

Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock

to XIN pin.

Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.

To input an externally generated clock, input it to XIN pin and open XOUT pin.

Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin.

Input "H" or "L" level signal or open.

Serial data output pin (Note 1)

Serial data input pin

Standard serial I/O mode 1: Serial clock input pin.

Standard serial I/O mode 2: Input "L" level signal.

Standard serial I/O mode 1: BUSY signal output pin

Standard serial I/O mode 2: Monitors the boot program operation check signal

output pin.

Input "H" or "L" level signal or open.

SEL signal input pin. Input "L" level signal.

CE signal input pin. Input "H" level signal.

Input "H" or "L" level signal or open.

VCC, VSS

IVCC

CNVSS

RESET

XIN

XOUT

VREF

P00 to P07

P10 to P13

P14

P15

P16

P17

P20, P21

P30

P31

P32 to P37

P40 to P47

P50 to P52

Power input

IVCC input

CNVSS input

Reset input

Clock input

Clock output

Reference voltage input

Input port P0

Input port P1

TXD output

RXD input

SCLK input

BUSY output

Input port P2

SEL input

CE input

Input port P3

Input port P4

Input port P5

Table 19.7 Pin functions (Flash memory standard serial I/O mode)

___________

Note 1: When using standard serial I/O mode 1, the TxD pin must be held high while the RESET pin is low.

Therefore, connect this pin to VCC via a resistor. Because this pin is directed for data output after

reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.

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