TMP93CS41 datasheet(186/248 Pages) TOSHIBA

186 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-184

6. Receiving buffer

To prevent overrun errors, the receiving buffer has a double buffer structure.

Received data is stored bit by bit in receiving buffer 1 (Shift register type). When 7

bits or 8 bits of data are stored in receiving buffer 1, the stored data is transferred to

receiving buffer 2 (SC0BUF), generating an interrupt INTRX0. The CPU reads only

receiving buffer 2 (SC0BUF). Even before the CPU has read receiving buffer 2

(SC0BUF), more received data can be stored in receiving buffer 1. However, unless

receiving buffer 2 (SC0BUF) is read before all the bits of the next data are received by

receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of

receiving buffer 1 will be lost, although the contents of receiving buffer 2 and

SC0CR<RB8> are still preserved.

The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit

UART mode are stored in SC0CR<RB8>.

In 9-bit UART mode, the wakeup function for the slave controller is enabled by

setting SC0MOD<WU> to “1”; and interrupt INTRX0 occurs only when SC0CR<RB8>

is set to 1.

7. Transmission counter

The transmission counter is a 4-bit binary counter which is used in Asynchronous

communication (UART) mode and, like a receiving counter, counts using the SIOCLK

clock. This generates a TXDCLK pulse every 16 clock pulses.

Figure 3.11.15 Generation of Transmission Clock

8. Transmission controller

•

I/O interface mode

In SCLK0 output mode with a setting of SC0CR<IOC>

= 0, the data in the

transmission buffer is output bit by bit to the TXD0 pin at the rising edge of the

shift clock which is output from the SCLK0 pin.

In SCLK0 Input mode with a setting of SC0CR<IOC>

= 1, the data in the

transmission buffer is output bit by bit to the TXD0 pin at the rising edge or falling

edge of the SCLK0 input, according to the setting of the SC0CR<SCLKS> register.

•

Asynchronous communication (UART) mode

When transmission data is written to the transmission buffer from the CPU,

transmission starts at the rising edge of the next TXDCLK pulse.

SIOCLK

TXDCLK

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