TMP93CS41 datasheet(188/248 Pages) TOSHIBA

188 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-186

9. Transmission buffer

The transmission buffer (SC0BUF) shifts out and sends the transmission data

written from the CPU in order starting with the least significant bit (LSB). When all

bits have been shifted out, the transmission buffer becomes empty and generates an

INTTX0 interrupt.

10. Parity control circuit

When the serial channel control register SC0CR<PE> is set to 1, it is possible to

transmit and receive data with parity. However, parity can be added only in 7-bit

UART or 8-bit UART modes. The SC0CR<EVEN> register can select even or odd

parity.

During transmission, parity is automatically generated according to the data written

to the transmission buffer SC0BUF. The data are transmitted after the parity bit is

stored in SC0BUF<TB7> in 7-bit UART mode, or in SC0MOD<TB8> in 8-bit UART

mode. <PE> and <EVEN> must be set before the transmission data is written to the

transmission buffer.

During receiving, data are shifted to the receiving buffer 1 and the parity is

automatically set after the data are transferred to the receiving buffer 2 (SC0BUF).

The parity bit is then compared with SC0BUF<RB7> in 7-bit UART mode, or with

SC0MOD<RB8> in 8-bit UART mode. If the bits do not match, a parity error occurs

and the SC0CR<PERR> flag is set.

11. Error flag

Three error flags are provided to increase the reliability of data reception.

1) Overrun error <OERR>

If all bits of the next datum are received in receiving buffer 1 while valid data is

stored in receiving buffer 2 (SC0BUF), an overrun error occurs.

2) Parity error <PERR>

The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is

compared with the parity bit received from the RXD pin. If they are not equal, a

parity error occurs.

3) Framing error <FERR>

The stop bit of the received data is sampled three times in the center of the

pulse. If the majority of the sampled values are “0”, a framing error occurs.

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