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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 182 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 182 Page - Toshiba Semiconductor |
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182 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-180 The selected clock (fFPH clock, fc/16 clock or fs clock) is divided by 4 and input to the prescaler. This selection is made by the prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to “00” and selects the fFPH clock input divided by 4. The baud rate generator selects between 4 clock inputs: The prescaler outputs φT0, φT2, φT8, and φT32. The prescaler can be run or stopped by the timer operation control register TRUN<PRRUN>. Counting starts when <PRRUN> is set to “1”. The prescaler is cleared to zero and stops operation when <PRRUN> is set to “0”. Resetting clears <PRRUN> to “0”, clearing the prescaler and stopping operation. When IDLE1 mode (in which only the oscillator operates) is used, set TRUN<PRRUN> to “0” to stop the prescaler before a HALT instruction is executed. |
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