TMP93CS41 datasheet(185/248 Pages) TOSHIBA

185 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-183

3. Serial clock generation circuit

This circuit generates the basic clock for transmitting and receiving data.

•

I/O interface mode

In SCLK output mode with a setting of SC0CR<IOC>

= “0”, the basic clock is

generated by dividing the output of the baud rate generator by 2, as described

previously. In SCLK Input mode with setting of SC0CR<IOC>

= “1”, the rising edge

or falling edge is detected, according to the setting of the SC0CR<SCLKS> register,

and used to generate the basic clock.

•

UART mode

The setting of SC0MOD<SC1:0> selects the baud rate generator clock, internal

clock

φ1 (Max 625 kbps at fc = 20 MHz) or the match detect signal from timer 0 as

the signal from which to generate the basic clock SIOCLK.

4. Receiving counter

The receiving counter is a 4-bit binary counter used in asynchronous communication

(UART) mode and counts up with the SIOCLK clock. A duration of 16 pulses of

SIOCLK are used for receiving 1 bit of data, and the data bit is sampled three times, at

the 7th, 8th, and 9th clock ticks.

Using these three samples, the received data is evaluated using the majority rule.

For example, if the sampled data bits are respectively “1”, “0” and “1” at the 7th, 8th,

and 9th clock ticks, the received data is evaluated as “1”. Sampled data “0”, “0” and 1 is

evaluated to be “0”.

5. Receiving control

•

I/O interface mode

In SCLK0 output mode with a setting of SC0CR<IOC>

= “0”, the RXD0 signal

will be sampled at the rising edge of the shift clock which is output to the SCLK0

pin.

In SCLK0 input mode with a setting of SC0CR<IOC>

= “1”, the RXD0 signal will

be sampled at the rising edge or falling edge of the SCLK0 input, according to the

setting of the SC0CR<SCLKS> register.

•

Asynchronous communication (UART) mode

The receiving control block has a circuit for detecting the start bit using the

majority rule. When two or more 0’s are detected out of 3 samples, it is recognized

as a start bit and the receiving operation is started.

The data being received is also evaluated using the majority rule.

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