TMP93CS41 datasheet(181/248 Pages) TOSHIBA

181 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-179

1. Prescaler

9-bit prescaler and prescaler clock selection registers generate input clocks for 8-bit

timer 0, 1, 16-bit timer 4, 5, and serial interface 0, 1.

Figure 3.11.15 shows the block diagram. Table 3.11.1 shows how the prescaler clock

is resolved into the baud rate generator.

Figure 3.11.14 Block Diagram of Prescaler

Table 3.11.1 Prescaler Clock Resolution for Baud Rate Generator

Prescaler Output Clock Resolution

Select System

Clock

<SYSCK>

Select Prescaler Clock

<PRCK1:0>

Gear Value

<GEAR2:0>

φT0

φT2

φT8

φT32

1 (fs)

XXX

fs/2

000 (fc)

fc/2

001 (fc/2)

fc/2

010 (fc/4)

fc/2

011 (fc/8)

fc/2

0 (fc)

(fFPH)

100 (fc/16)

fc/2

XXX

(Low-frequency clock)

XXX

−

fs/2

XXX

(fc/16 clock)

XXX

−

fc/2

XXX: Don’t care,

−: Invalid

Note: The fc/16 clock cannot be used as a prescaler clock when the fs clock is used as a system clock.

To 8-bit timer 0, 1

9-bit prescaler

XT1

φT1

φT4

φT16

φT256

fFPH

To CPU

÷4 ÷8 ÷16

÷2

SYSCR1<GEAR2:0>

SYSCR1<SYSCK>

fc fc/2

fc/4 fc/8 fc/16

SYSCR0

<PRCK1:0>

Run/stop

& clear

TRUN<PRRUN>

2 4

128

256 512

φT1

φT4

φT16

To 16-bit timer 4, 5

φ1

φT0

φT2

φT8

φT32

To serial interface

0, 1

To 5-bit prescaler

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