TMP93CS41 datasheet(114/248 Pages) TOSHIBA

114 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-112

In this mode, the value of the register buffer will be shifted into TREG0 if a 2n

− 1

overflow is detected while the double buffer of TREG0 is enabled.

Use of the double buffer makes easy the handling of small-duty waves.

Figure 3.7.15 Operation of Register Buffer

Example: To output the following PWM waves to the TO1 pin at fc

= 20 MHz.

Clock conditions

System clock:

High frequency (fc)

Clock gear:

1 (fc)

Prescaler clock:

fFPH

To implement a PWM cycle of 50.8

µs by utilizing φT1 = 0.4 µs (at fc = 20 MHz),

50.8

µs ÷ 0.4 µs = 127 = 2n − 1

Consequently, n should be set to 7.

As the period of low level is 28.8

µs, for φT1 = 0.4 µs,

set the following value for TREG0.

28.8

µs ÷ 0.4 µs = 72 = 48H

MSB

LSB

TRUN

← − X − − − − − 0

Stop timer 0 and clear it.

TMOD

← 1 1 1 0 − − 01

Set 8-bit PWM mode (cycle: 2

− 1) and select φT1 as the

input clock.

TREG0

← 0 1 0 0 1 0 0 0

Writes “48H”.

TFFCR

← X X X X 1 0 1 X

Clear TFF1, enable the inversion and double buffer.

P7CR

← X X X X − − 1 −

P7FC

← X X X X −− 1X

Set P71 as the TO1 pin.

TRUN

← 1 X − − − − − 1

Start timer 0 counting.

X: Don’t care,

−: No change

28.8

µs

50.8

µs

Up counter

= Q1

Up counter

= Q2

Shift into TREG0

TREG0 (Register buffer) write

Match with TREG0

− 1 overflow

TREG 0

(Value to be compared)

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