TMP93CS41 datasheet(109/248 Pages) TOSHIBA

109 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-107

3. Making timer 1 count up by matching the signal from the timer 0 comparator

Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to

timer 1.

Figure 3.7.8 Timer 1 Count Up Regulated by Timer 0

(2) 16-bit timer mode

A 16-bit interval timer is configured by using timer 0 and timer 1 as a pair.

Setting timer mode register TMOD<T10M1:0> to “01” establishes a 16-bit timer mode.

When set in 16-bit timer mode, the overflow output of timer 0 will become the input clock

of timer 1, regardless of the set value of TMOD<T1CLK1:0>. Table 3.7.1 shows the selection

of timer 0 input clock.

The lower 8 bits of the timer (interrupt) cycle are set by the timer register TREG0, and

the upper 8 bits are set by TREG1. Note that TREG0 always must be set first. (Writing data

into TREG0 disables the comparator temporarily, and the comparator is restarted by

writing data into TREG1.)

Setting example: To generate an interrupt INTT1 every 0.4 seconds at fc

= 20 MHz, set

the following values for timer registers TREG0 and TREG1.

Clock condition

System clock:

High frequency (fc)

Clock gear:

1 (fc)

Prescaler clock:

fFPH

When counting with the

φT16 input clock (6.4 µs at 20 MHz)

0.4 s

÷ 6.4 µs = 62500 = F424H

Therefore, set TREG1

= F4H and TREG0 = 24H, respectively.

Comparator output

(Timer 0 match)

Timer 0 up counter

(when TREG0

= 5)

Timer 1 up counter

(when TREG1

= 2)

Timer 1 matching output

234

512

345

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