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TMP93CS41 датащи(PDF) 106 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 106 Page - Toshiba Semiconductor |
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106 / 248 page ![]() TMP93CS40/TMP93CS41 20004-02-10 93CS40-104 7 6 5 4 3 2 1 0 Bit symbol DBEN TFF1C1 TFF1C0 TFF1IE TFF1IS Read/Write R/W W R/W After reset 0 1 1 0 0 Function Double buffer 0: Disable 1: Enable 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don’t care TFF1 inversion trigger 0: Disable 1: Enable TFF1 inversion source 0: Timer 0 1: Timer 1 Note: TFFCR<bit7:5>, <bit3:2> are read as “1”. Figure 3.7.6 Timer Flip-Flop Control Register (TFFCR) TMOD<T10M1:0> <TFF1IS> 00 01 10 11 0 Inversion by timer 0 match signal 1 Inversion by timer 1 match signal 16-bit timer mode Inversion by match signal PPG mode Inversion by matching signals of both timer 0 and timer 1 PWM mode Inversion by matching and overflow signals of timer 0 Select inverse signal of timer F/F1 (“Don’t care” except in 8-bit timer mode) 0 Disable inversion 1 Enable inversion Inversion of timer flip-flop 1 (TFF1) 00 Invert the value of TFF1 (Software inversion) 01 Set TFF1 to “1”. 10 Clear TFF1 to “0”. 11 Don’t care Control of timer flip-flop 1 (TFF1) Double buffer control of TREG0 0 Disable double buffer 1 Enable double buffer TFFCR (0025H) |
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