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ADC3683 датащи(PDF) 65 Page - Texas Instruments

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номер детали ADC3683
подробное описание детали  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 датащи(HTML) 65 Page - Texas Instruments

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Figure 9-24. Register 0x61..0x88
7
6
5
4
3
2
1
0
OUTPUT BIT MAPPER CHB
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-28. Register 0x61..0x88 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OUTPUT BIT MAPPER CHB
R/W
0
These registers are used to reorder the output data bus. See the
Section 7.3.5.3 on how to program it.
Figure 9-25. Register 0x8F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FORMAT A
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-29. Register 0x8F Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1
FORMAT A
R/W
0
This bit sets the output data format for channel A.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
Figure 9-26. Register 0x92
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FORMAT B
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-30. Register 0x92 Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1
FORMAT B
R/W
0
This bit sets the output data format for channel B.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
Figure 9-27. Register 0x244
7
6
5
4
3
2
1
0
0
0
DCLKIN Vcm
0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-31. Register 0x244 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
DCLKIN Vcm
R/W
0
This bit sets the common mode source for DCLKIN.
0: Must supply external DCLKIN Vcm
1:DCLKIN Vcm is based internally to 1.2V
4-0
0
R/W
0
Must write 0
www.ti.com
ADC3683-SP
SBASAB5 – MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: ADC3683-SP



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