ADC3683 datasheet(42/70 Pages) TI1

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7.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI); however, the

device can operate in a default configuration without requiring the SPI interface. The power down function as

well as internal or external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).

Note

The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.

7.5.1 Configuration using PINs only

The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100kΩ

pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating. When using

a voltage divider to set the REFBUF voltage (R1 and R2 in Figure 7-47), resistor values < 5kΩ should be used.

100 k

REFBUF

AVDD

Figure 7-47. Configuration of external voltage on REFBUF pin

Table 7-11. REFBUF voltage levels control voltage reference selection

REFBUF VOLTAGE

VOLTAGE REFERENCE OPTION

CLOCKING OPTION

> 1.7V (Default)

External reference

Differential clock input

1.2V (1.15-1.25V)

External 1.2V input on REFBUF pin using internal gain buffer

Differential clock input

0.5 - 0.7V

Internal reference

Differential clock input

< 0.1V

Internal reference

Single ended clock input

Table 7-12. REFBUF voltage levels control voltage reference selection

REFBUF VOLTAGE

VOLTAGE REFERENCE OPTION

CLOCKING OPTION

> 1.7V (Default)

External reference

Differential clock input

1.2V (1.15-1.25V)

External 1.2V input on REFBUF pin using internal gain buffer

Differential clock input

0.5 - 0.7V

Internal reference

Differential clock input

< 0.1V

Internal reference

Single ended clock input

7.5.2 Configuration using the SPI interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting

bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when

SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.

When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples

of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz

down to low speeds (of a few hertz), and with a non-50% SCLK duty cycle.

ADC3683-SP

SBASAB5 – MARCH 2024

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