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ADC3683 датащи(PDF) 37 Page - Texas Instruments |
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ADC3683 датащи(HTML) 37 Page - Texas Instruments |
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37 / 70 page ![]() 7.3.5.3.3 ½-Wire Mode The output is only lane DA0 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). This covers 2 samples (one for chA, one for chB) as shown below. A duplicate can be created on DB0 as well (using addresses shown in Figure 7-43) to have a redundant output. Lane DB0 must be powered up. DB0 DA0 (default) 0x60 0x5F 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D 14-bit 20-bit 18-bit 16-bit 0x4C 0x4B 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x88 0x87 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75 0x74 0x73 0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61 20-bit 18-bit 16-bit 14-bit ... ... ... ... Figure 7-43. 1/2-wire output bit mapping www.ti.com ADC3683-SP SBASAB5 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: ADC3683-SP |
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