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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC3683 датащи(PDF) 36 Page - Texas Instruments |
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ADC3683 датащи(HTML) 36 Page - Texas Instruments |
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36 / 70 page  7.3.5.3.1 2-Wire Mode In this mode, both the current and the previous sample have to be used in the address space as shown in Figure 7-40. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (gray back ground), which can be skipped if not used. Previous Sample DB1 DB0 Current Sample DA1 DA0 0x5F 0x60 0x60 0x5F 0x5D 0x5E 0x5E 0x5D 0x5B 0x5C 0x5C 0x5B 0x59 0x5A 0x5A 0x59 0x57 0x58 0x58 0x57 0x55 0x56 0x56 0x55 0x53 0x54 0x54 0x53 0x51 0x52 0x52 0x51 0x4F 0x50 0x50 0x4F 0x4D 0x4E 0x4E 0x4D 20-bit 18-bit 16-bit 14-bit 20-bit 18-bit 16-bit 14-bit 0x4B 0x4C 0x4C 0x4B 0x49 0x4A 0x4A 0x49 0x47 0x48 0x48 0x47 0x45 0x46 0x46 0x45 0x43 0x44 0x44 0x43 0x41 0x42 0x42 0x41 0x3F 0x40 0x40 0x3F 0x3D 0x3E 0x3E 0x3D 0x3B 0x3C 0x3C 0x3B 0x39 0x3A 0x3A 0x39 0x87 0x88 0x88 0x87 0x85 0x86 0x85 0x86 0x83 0x84 0x83 0x84 0x81 0x82 0x81 0x82 0x7F 0x80 0x7F 0x80 0x7D 0x7E 0x7E 0x7D 0x7B 0x7C 0x7C 0x7B 0x79 0x7A 0x7A 0x79 0x77 0x78 0x78 0x77 0x75 0x76 0x76 0x75 0x73 0x74 0x74 0x73 0x71 0x72 0x72 0x71 0x6F 0x70 0x70 0x6F 0x6D 0x6E 0x6E 0x6D 0x6B 0x6C 0x6C 0x6B 0x69 0x6A 0x6A 0x69 0x67 0x68 0x68 0x67 0x65 0x66 0x66 0x65 0x63 0x64 0x64 0x63 0x61 0x62 0x62 0x61 14/18-bit 14/18-bit 16/20-bit 16/20-bit 14/18-bit 16/20-bit 14/18-bit 16/20-bit Figure 7-40. 2-wire output bit mapper In the following example (Figure 7-41), the 16-bit 2-wire serial output is reordered to where lane DA1/DB1 carries the 8 MSB and lane DA0/DB0 carries 8 LSBs. DA1 D19A (0x60 0x2D) DA0 D11A (0x4C 0x1D) D18A (0x5F 0x2C) D10A (0x4B 0x1C) D17A (0x5E 0x27) D9A (0x4A 0x17) D16A (0x5D 0x26) D8A (0x49 0x16) DB1 D19B (0x88 0x29) DB0 D11B (0x74 0x19) D18B (0x87 0x28) D10B (0x73 0x18) D17B (0x86 0x23) D9B (0x72 0x13) D16B (0x85 0x22) D8B (0x71 0x12) D15A (0x5C 0x25) D7A (0x48 0x15) D14A (0x5B 0x24) D6A (0x47 0x14) D13A (0x5A 0x1F) D5A (0x46 0x0F) D12A (0x59 0x1E) D4A (0x45 0x0E) D15B (0x84 0x21) D7B (0x70 0x11) D14B (0x83 0x20) D6B (0x6F 0x10) D13B (0x82 0x1B) D5B (0x6E 0x0B) D12B (0x81 0x1A) D4B (0x6D 0x0A) D19A (0x56 0x6D) D11A (0x42 0x5D) D18A (0x55 0x6C) D10A (0x41 0x5C) D17A (0x54 0x67) D9A (0x40 0x57) D16A (0x53 0x66) D8A (0x39 0x56) D19B (0x7E 0x69) D11B (0x6A 0x59) D18B (0x7D 0x68) D10B (0x69 0x58) D17B (0x7C 0x63) D9B (0x68 0x53) D16B (0x7B 0x62) D8B (0x67 0x52) D15A (0x52 0x65) D7A (0x38 0x55) D14A (0x51 0x64) D6A (0x37 0x54) D13A (0x50 0x5F) D5A (0x36 0x4F) D12A (0x4F 0x5E) D4A (0x35 0x4E) D15B (0x7A 0x61) D7B (0x66 0x51) D14B (0x79 0x60) D6B (0x65 0x50) D13B (0x78 0x5B) D5B (0x64 0x4B) D12B (0x77 0x5A) D4B (0x63 0x4A) Previous Sample Current Sample Figure 7-41. Example: 2-wire output bit mapping 7.3.5.3.2 1-Wire Mode Only the ‘current’ sample needs to programmed in the address space. A duplicated can be created on DA1/DB1 as well (using addresses shown below) to have a redundant output. Lane DA1/DB1 needs to be powered up. DB1 DB0 (default) DA1 DA0 (default) 0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D 14-bit 20-bit 18-bit 16-bit 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x88 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80 0x7F 0x7E 0x7D 0x7C 0x7B 0x7A 0x79 0x78 0x77 0x76 0x75 0x74 0x73 0x72 0x71 0x70 0x6F 0x6E 0x6D 0x6C 0x6B 0x6A 0x69 0x68 0x67 0x66 0x65 0x64 0x63 0x62 0x61 Figure 7-42. 1-wire output bit mapping ADC3683-SP SBASAB5 – MARCH 2024 www.ti.com 36 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3683-SP |
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