ADC3683 datasheet(33/70 Pages) TI1

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7.3.5 Digital Interface

The serial LVDS interface supports the data output with 2-wire, 1-wire and 1/2-wire operation. The actual data

output rate depends on the output resolution and number of lanes used.

The ADC3683-SP requires an external serial LVDS clock input (DCLKIN), which is used to transmit the data

out of the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling

clock must meet requirements in the timing diagrams in Section 6. The SLVDS interface is configured using SPI

7.3.5.1 Output Formatter

The digital output interface uses a flexible output bit mapper (Figure 7-36). The bit mapper takes the 18-bit

output directly from the ADC or from the digital decimation filter block and reformats it to a resolution of

14,16,18 or 20-bit. The output serialization factor is adjusted accordingly for 2-, 1- and 1/2-wire interface modes.

The maximum SLVDS interface output data rate can not be exceeded independent of output resolution or

serialization factor.

For 14 and 16-bit output resolution, the LSBs are truncated during the reformatting. With 20-bit output, in bypass

mode two 0s are added in place of the two LSBs while in decimation mode. The digital averaging mode with the

full 20-bit output is used.

NCO

TEST

PATTERN

Output

Formatter

14/16/18/

20-bit

DIG

I/F

Output

Bit Mapper

Output

Scrambler

Figure 7-36. Interface Output Bit Mapper

Table 7-6 provides an overview for the resulting serialization factor depending on output resolution and output

modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output

resolution to 16-bit, 2-wire mode for example results in DCLKIN = FS * 4 instead of * 4.5.

The programming sequence for changing the output interface and/or resolution from default settings is shown in

Section 7.3.5.4.

Table 7-6. Serialization Factor vs Output Resolution for Different Output Modes

OUTPUT

RESOLUTION

Interface

SERIALIZATION

FCLK

DCLKIN

DCLK

D0/D1

14-bit

2-Wire

FS/2

FS* 3.5

FS* 7

1-Wire

14x

FS* 7

FS* 14

1/2-Wire

28x

FS* 14

FS* 28

16-bit

2-Wire

FS/2

FS* 4

FS* 8

1-Wire

16x

FS* 8

FS* 16

1/2-Wire

32x

FS* 16

FS* 32

18-bit (default)

2-Wire

FS/2

FS* 4.5

FS* 9

1-Wire

18x

FS* 9

FS* 18

1/2-Wire

36x

FS* 18

FS* 36

20-bit

2-Wire

10x

FS/2

FS* 5

FS* 10

1-Wire

20x

FS* 10

FS* 20

1/2-Wire

40x

FS* 20

FS* 40

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ADC3683-SP

SBASAB5 – MARCH 2024

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