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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC3683 датащи(PDF) 61 Page - Texas Instruments |
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ADC3683 датащи(HTML) 61 Page - Texas Instruments |
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61 / 70 page  Figure 9-15. Register 0x24 7 6 5 4 3 2 1 0 0 0 CH AVG EN DDC MUX DIG BYP DDC EN 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 9-19. Register 0x24 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 CH AVG EN R/W 0 Averages the output of ADC channel A and channel B together. The DDC MUX has to be enabled and set to '11'. The decimation filter needs to be enabled and set to bypass (fullrate output) or decimation and DIG BYP set to 1. 0: Channel averaging feature disabled 1: Output of channel A and channel B are averaged: (A+B)/2. 4-3 DDC MUX R/W 0 Configures DDC MUX in front of the decimation filter. 00: ADC channel A connected to DDC A; ADC Channel B connected to DDC B 01: ADC channel A connected to DDC A and DDC B. 10: ADC channel B connected to DDC A and DDC B. 11: Output of ADC averaging block (see CH AVG EN) given to DDC A and DDC B. 2 DIG BYP R/W 0 This bit needs to be set to enable digital features block which includes decimation. 0: Digital feature block bypassed - lowest latency 1: Data path includes digital features 1 DDC EN R/W 0 Enables internal decimation filter for both channels 0: DDC disabled. 1: DDC enabled. 0 0 R/W 0 Must write 0 N DDC MUX DECIMATION DDC DIG BYP To output interface N DDC To output interface CH Average Figure 9-16. Register Control for Digital Features www.ti.com ADC3683-SP SBASAB5 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: ADC3683-SP |
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