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ADC3683 датащи(PDF) 40 Page - Texas Instruments |
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ADC3683 датащи(HTML) 40 Page - Texas Instruments |
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40 / 70 page ![]() 7.4 Device Functional Modes 7.4.1 Normal Operation In normal operating mode, the entire ADC full-scale range gets converted to a digital output with 18-bit resolution. 7.4.2 Power Down Options A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is an internal pull-down 21kΩ resistor on the PDN/SYNC input pin and the pin is active high, so the pin must be pulled high externally to enter global power down mode. The SPI register map provides the capability to enable or disable individual blocks directly or via PDN pin mask. The trade off power consumption vs wake up time as shown in Table 7-10. AIN CLK VREF 1.2V REF REFBUF Digital Downconverter Dig I/F ADC N NCO ADC N NCO Crosspoint Switch BIN Figure 7-45. Power Down Configurations Table 7-10. Overview of Power Down Options Function/ Register PDN via SPI Mask for Global PDN Feature - Default Power Impact Wake-up time Comment ADC Yes - Enabled Both ADC channels are included in Global PDN automatically Reference gain amplifier Yes Yes Enabled ~ 0.4mA ~3us Should only be powered down in power down state. Internal 1.2V reference Yes External ref ~ 1-3.5mA ~3ms Internal or external reference selection is available through SPI and REFBUF pin. Clock buffer Yes Differential clock ~ 1mA n/a Single ended clock input saves approximately 1mA compared to differential. Some programmability is available through the REFBUF pin. Output interface drivers Yes - Enabled varies n/a Depending on output interface mode, unused output drivers can be powered down for maximum power savings Decimation filter Yes - Disabled see electrical table n/a ADC3683-SP SBASAB5 – MARCH 2024 www.ti.com 40 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3683-SP |
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