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ADC3683 датащи(PDF) 60 Page - Texas Instruments

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номер детали ADC3683
подробное описание детали  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 датащи(HTML) 60 Page - Texas Instruments

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Figure 9-13. Register 0x1E
7
6
5
4
3
2
1
0
0
0
0
0
LVDS DATA DEL
LVDS DCLK DEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-16. Register 0x1E Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
R/W
0
Must write 0
3-2
LVDS DATA DEL
R/W
00
These bits adjust the output timing of the SLVDS output data.
00: no delay
01: Data advanced by 50ps
10: Data delayed by 50ps
11: Data delayed by 100ps
1-0
LVDS DCLK DEL
R/W
00
These bits adjust the output timing of the SLVDS DCLK output.
00: no delay
01: DCLK advanced by 50ps
10: DCLK delayed by 50ps
11: DCLK delayed by 100ps
Figure 9-14. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-17. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 9-18 shows the proper
FCLK pattern values for 1-wire and 1/2-wire in real/complex
decimation.
Table 9-18. FCLK Pattern for different resolution based on interface
DECIMATION
OUTPUT RESOLUTION
2-WIRE
1-WIRE
1/2-WIRE
REAL DECIMATION
14-bit
Use Default
0xFE000
Use Default
16-bit
0xFF000
18-bit
0xFF800
20-bit
0xFFC00
COMPLEX
DECIMATION
14-bit
0xFFFFF
0xFFFFF
16-bit
18-bit
20-bit
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
60
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Product Folder Links: ADC3683-SP



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